Contacts and Location
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Riga Technical University
Office of Vice-Rector for Research
Vice Rector for Science - Latvia, Rīga
HDL Verifier™ automates Verilog® and VHDL® design verification using HDL simulators and FPGA hardware-in-the-loop testbenches. It provides interfaces that link MATLAB® and Simulink® with Cadence® Incisive®, Mentor Graphics® ModelSim®, and Questa® HDL simulators. It also supports FPGA-in-the-loop verification with Xilinx® and Altera® FPGA boards.
HDL Verifier automates verification by using MATLAB or Simulink to stimulate your HDL code and analyze its response. This approach eliminates the need to author standalone Verilog or VHDL test benches.